The NAND gate networks shown in Fig. 2.5 are typical MSI-complexity ICs.

Remembering that the output of a NAND gate is logic 0 only when all its inputs are logic 1 (see Fig. 1.2(c) on p. 13) then we see that for any combination of the select inputs B A (2¹ 2⁰) in Fig. 2.5(a) only one gate will go to logic 0.

The 74LS138 of Fig. 2.5(b) is similar, but implements a 3- to 8-line decoder function.

In Fig. 2.25 a modulo-4 counter is used to address one section of a 74LS139 2- to 4-line decoder; see Fig. 2.5(a).